Samsung reportedly ahead of TSMC with next-gen panel-level packaging semiconductor tech
Samsung is reportedly ahead of next-generation panel-level packaging (PLP) in its never-ending semiconductor battle with TSMC.
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In a new report from Business Korea, we’re hearing that Samsung is making “significant strides” in the semiconductor packaging industry, “positioning itself ahead of TSMC in the Panel Level Packaging (PLP) field”. This new development comes after Samsung acquired the PLP business from Samsung Electro-Mechanics back in 2019 for around $581 million.
During Samsung’s recent shareholders meeting in March 2024, the former head of Samsung Electronics’ semiconductor (DS) division, Kyung Kye-hyun, elaborated on the necessity of PLP technology. He said: “AI semiconductor dies (rectangular pieces with circuits) are typically 600mm x 600mm or 800mm x 800mm in size, necessitating technologies like PLP,” he explained, adding, “Samsung Electronics is also developing and collaborating with clients”.
TSMC started its research into panel-level packaging recently, including Fan-Out (FO)-PLP, which uses rectangular printed circuit boards (PCBs) versus traditionally round wafers. Nikkei Asia reported on this recently, where they said: “TSMC’s research is still in its early stages and mass production is expected to take several years. TSMC’s entry into research, despite its previous skepticism about using rectangular PCBs, signifies an ‘important technological shift“.
Market research firm IDC experts NVIDIA requires half to TSMC’s entire CoWoS advanced packaging technology in order to fulfill current-gen Hopper H100, B200 and next-gen Blackwell B100, B200, and GB200 AI chips… as well as NVIDIA’s future-gen Rubin R100 that’s coming with ultra-gen HBM4 memory in 2025.
TSMC plans to double CoWoS advanced packaging production capacity by the end of 2024, but NVIDIA has competition from AMD and Broadcom for TSMC’s volume CoWoS production. NVIDIA has the AI GPU weight in the market to pull as much as it wants from TSMC, it will need it to meet demand in 2025 and beyond.
Panel-level packaging, CoWoS, and FO-PLP semiconductor technology are now emerging as alternatives to the most advanced packaging on Earth right now. DigiTimes recently reported from its industry sources that “NVIDIA plans to adopt FO-PLP technology for server AI semiconductors in response to TMSC’s packaging supply constraints”.
Tawanese market research outlet TrendForce recently said: “PLP has emerged as a new battleground for TSMC, Samsung Electronics, and Intel”.
